System of conversion and computing circuits based on the constant-sum unimodular p-adic number



Nov. 3, 1970 RYOTA SUEKANE .SYSTEM OF CONVERSION AND COMPUTING CIRCUITS BASED ON THE CONSTANT-SUM UNIMODULAR P-ADIC NUMBER Filed April 22, 1969 10 Sheets-Sheet 5 e a 0 3 U Nov. 3, 1970 RYOTA SUEKANE 3,538,314

SYSTEM OF CONVERSION AND COMPUTING CIRCUITS BASED ON THE CONSTANT-SUM UNIMODULAR P-ADIC NUMBER Filed April 22, 1969 10 Sheets-Sheet 4 ffiy-o (A) fiy- (B) w mwx b'n b'Il-I bn-2 bn-a b0 b-I Pam I N VEN TOR.

10 Sheets-Sheet 5 RYOTA SUEKANE INVENTOR. WW BY CONSTANT-SUM UNIMODULAR P-ADIC NUMBER SYSTEM OF CONVERSION AND COMPUTING CIRCUITS BASED ON THE Nov. 3, 1970 Filed April 22, 1969 NOV; 3, 1970 RYQTA SUEKANE 3,538,314

SYSTEM OF CONVERSION AND COMPUTING CIRGUITS BASED ON THE CONSTANT-SUM UNIMODULAR P-ADIG NUMBER Filed April 22, 1969 7 l0 Sheets-Sheet 6 INVENTOR.

Nov. 3, 1970 RYOTA SUEKANE SYSTEM OF CONVERSION AND COMPUTING CIRCUITS BASED ON THE CONSTANT-SUM UNIMODULAR P-ADIC NUMBER Filed April 22, 1969 10 Sheets-Sheet '7 AS AvH QK AS En Ra ium INVENTOR.

Nov.,3, 1970 RYOTA SUEKANE 3,538,314

SYSTEM OF CONVERSION AND COMPUTING CIRCUITS BASED-v ON THE CONSTANT-SUM UNIMODULAR P-ADIC NUMBER Filed April 22, 1969 10 Sheets-Sheet 8 8 o s 9% $5 Q Q R 9 an 5M INVEN'I'OR.

RYOTA SUEKANE 3,538,314

SYSTEM OF- CONVERSION AND COMPUTING CIRCUITS BASED ON THE CONSTANT-SUM UNIMODULAR P ADIC NUMBER Filed April 22, 1969 10- Sheets-Sheet 9 W N EN iv a Q INVENT OR.

NOV- 1970 RYOTA SUEKANE SYSTEM OF CONVERSION AND COMPUTING CIRCUITS BASED ON THE CONSTANT-SUM UNIMODULAR P-A'DIC NUMBER 10 Sheets-Sheet 10 Filed April 22, 1969 llll. 1

INVENTOR.

gum 1 United States Patent US. Cl. 235153 5 Claims ABSTRACT OF THE DISCLOSURE The present invention relates to a system containing circuits for converting a conventional p-adic number to a novel constant-sum unimodular p-adic number, circuits for converting a constant-sum unimodular p-adic number to an ordinary p-adic number and circuits for the addition of constant-sum unimodular p-adic numbers, thereby enabling the integration of the adder and checker.

This is a continuation-in-part of my copending application Ser. No. 449,714, filed Apr. 21, 1965, now abandoned.

The present invention relates to a system of conversion and computing circuits based on a constant-sum unimodular p-adic number which is converted from a conventional p-adic number used in digital computers and information processing devices. More particularly, this invention relates to a system containing circuits for converting a conventional p-adic number to a novel constantsum unimodular p-adic number, circuits for converting a constant-sum unimodular p-adic number to an ordinary p-adic number and circuits for the addition of constantsum unimodular p-adic numbers, thereby enabling the integration of the adder and checker.

The term p-adic is herein defined to be the number sysetm with the base p, i.e., Z-adic is the binary system; ll-acidic is the ternary system; -acidic is the decimal system; etc.

In the conventional information processing device, especially in the digital computer, the applicable number codes have been limited since the conventional number codes are basically constructed on the ordinary p-adic number code. Accordingly, in the conventional system, for example, the computer control of a plant, a necessary information processing according to the conventional system was obtained by the calculation of the p-adic number converted from a binary unit distance code corresponding to the analogue quantity detected in the respective points in the plant.

The applicable unit distance code for the above system is limited to the Gray code, and any other codes could not be applied to date. A block diagram of a prior art conventional system is shown in FIG. 1 in which a 'digi tized analogue quantity detected from the plant is transmitted into a computing circuit. An error detection of the conventional computing circuit in this information processing device is constructed with three circuits. One circuit is a computing circuit operating on numerical values in conventional binary numbers and it computes the error detecting parity digit Q to be attached to the number which represents the output value being computed from input digits. Another circuit compares error detecting digit P to be attached to the aforementioned output value with Q. An error in the computation is deice tected when P and Q do not coincide. Another means of error detecting of computing circuits is performed by operating more than two identical computers or by operating the computer repeatedly, however, both systems are uneconomical.

It is one object of the present invention to provide a conversion circuit and a computing circuit which is not only capable of detecting errors from the constant-sum of the output value without especially attaching any other additional circuit as used in the conventional method but also which is able to use various codes other than the p-adic number without employing a usual code of the p-adic number but using the constant-sum unimodular p-adic system. With the above and other objects in view which will become apparent in the following detailed description, the present invention will be clearly understood in connection with the accompanying drawings, in which:

FIG. 1 is a conventional computer control system for a plant wherein the analogue value detected by a detector as a value to be controlled is digitalized and the digital value is treated in an electronic computer;

FIG. 2 is the conventional error check system for an operation circuit (adder circuit) of a computer;

FIG. 3 is a block diagram of an embodiment of the overall system of the present invention;

FIG. 4 is a similar diagram to FIG. 3, in which the present system is shown in more detail with symbolic circuit components;

FIG. 5 is a symbolically represented example of the p-adic number to constant-sum cyclic p-adic number converter in FIGS. 3 or 4, in which FIG. 5(A) shows a parallel conversion circuit and FIG. 5(B) shows a series conversion circuit;

FIG. 6 is symbolically represented constant-sum cyclic p-adic number to ordinary p-adic number converter in FIGS. 3 and 4;

FIG. 7 shows the contact matrix circuit for each of the symbolic circuit components of the 3-adic system (ternary system);

FIG. 8 shows the same circuit as FIG. 7 for the 5- adic system (quinary system);

FIG. 9 shows an embodiment of the present detection circuit for a system using 3-adic number of three digits; and

FIGS. 10(a)-l0(e) show the overall circuitof the embodiment of FIG. 3, using contact matrix circuits of two digits in the 3-adic system.

Returning now to the drawings, FIG. 1 is a conventional computer control system for a plant and when the system of the present invention is employed in this typical computer control system the circuit portion encircled by the dotted line can be deleted.

FIG. 2 shows the conventional system of an electronic computer and as mentioned above the error detection circuit of this computer enclosed by the dotted line can also be deleted by applying the system of the present invention.

In order to facilitate the present invention, it will be described with respect to the mathematical theory of the constant-sum which is one of the essential features of the constant-sum p-adic number and the mutal relation between the conventional p-adic numbers and the present constant-sum unimodular p-adic numbers.

When an aribitrary number N is to be symbolized by an ordinary p-adic number system, the following polynomial expansion is used with coefficients of N in p:

and is used, where, A ,A A ,A are integers modulo p, that is to say, are p-type numbers represented by the integers from to p i.e. O-p Now, suppose the vector,

is obtained from the linear transformation, on the integer modulo p to which a constant digit a representing a constant number equal to any integral number O-p is attached or added to the right side of the ordered group of (2), i.e., at the right side of a through a(n+2)x(n+2) unimodular matrix (whose determinant is :1).

0,n n, n-1 s ADJ) n 1 n-1,n n1,-n1 n--1,01 n--1,-1

1,n -1,n-1 -1,o -1,*1

to a vector n ir-4 1, 0 4) Thus, the representation by the constant-sum unimodular p-adic number corresponding to p-adic number, which represents number N, is obtained as Formula 3.

Now supposing the computation to obtain each component of the vector of the Formula 3; through matrix (5) from (4), is performed on the integer modulo p, values of respectibe b are obtained by the formula as Since the unimodular matrix usually retains the corresponding inverse matrix, the constant-sum unimodular p-adic number which represents the number N may be converted into the p-adic number (4) which represents the number N by application of the inverse unimodular matrix,

Each component of vector (4) can be represented by components involved in vector (3) and matrix (7).

Thus, individual values of A can be obtained from the following formulas:

p-adic number which represents the number N which is 4 the basic constituents of both the conversion circuit and computing circuit of the present invention.

Particularly, the present invention as described above is fundamentally featured that the present constant-sum established for the arithmetic operation is not only limited to one supplemental digit, but also effective to a plurality of supplemental digits.

An adding operation of the constant-sum unimodular p-adic number which constitutes an essential part of the computing circuit based on the constant-sum unimodular p-adic number of the present invention will be described.

Let two numbers be X, Y, the sum of which is Z (hereinafter referred to as output or response), and to their representation in p-adic number is added or attached the constant-sum digit, x y and z to the right side of x y and z as below,

=()n, n-1 Y1 Y0 3 -1) Z=z z z Z1, z z (11) and also the representation of these p-adic numbers are constant-sum unimodular p-adic number,

ten down by p-adic number system with the exception of the constant digital portion,

faw x 23 Augend X y y y y Adder Y C C C Carry C Z Z Z Z Z Sum Z (13) will be established.

But 2, in the i digit of the sum Z is the sum modulo p of the three digits x and y in the i digit appeared in the augend and the addend together with C, carried from the neighbouring lower digital position being represented y l i+ i+ i-1 (Modulo P) The systematic addition of the constant-sum unimodular p-adic number corresponding to the Formula 13 is established.

In this case, the carry vector of the Formula 15 in the constant-sum unimodular p-adic number n n-l 1: 0, 1

is what has been obtained through the linear transformation of the carry vector by the unimodular matrix mentioned in (5).

In addition, individual number Z in each digit of the sum Z in the constant-sum unimodular p-adic number of the Formula 15 is obtained from the following formula '1= '1+ '1+ '1 1 (Modulo P) i n i,n+ -1 i,n1+ o i,0+ 1 i1 by linear formation of Formula 5 incorporating n n1 1, 0, and rm i,n-1 i,o 1,-1

If Z Z Z Z which are obtained varying 1 within the range between n to -l in the Formula 14 are substituted into Formula 19, a formula which represents a general term can be obtained.

If the Formula 20 is rearranged after multiplication of the numbers into the blankets, the following formula The three terms in parenthesis in formula (21) are equivalent to numbers x,, y, in the respectivei digits in Formulas 9' and 10' which have been symbolized by converting the augend X and addend Y of Formulas 9 and 10, which were represented by the p-adic system indication into the constant-sum unimodular p-adic number system.

Further, the last parenthesis shows the component of the i digit represented by the constant-sum unimodular p-adic number obtained from multiplication of the carry vector C represented by the p-adic number of the synthematic addition mentioned in Formula 13 and the unimodular matrix shown in the Formula 5. That is to say, respective parenthesis in the Formula 21 are individually equialent with x y,, d,,

Thus, in order to construct an adding circuit of the constant-sum unimodular p-adic number according to the present invention, it is necessary to provide the adding circuit of modulo p of the three inputs having either a spatial cyclic property or a temporal cyclic property or such another method in which a supplemental circuit uses the adding circuit modulo p of the three inputs repeatedly. For executing the later method, the augends and the addends of the three inputs are applied at the state of the constant-sum unimodular p-adic indication and, at the same time, each component of the vector (d d d a' is applied by converting the carrying vector (C C,, C C of the p-adic number by means of the unimodular matrix The aforementioned theory of the adding circuit is applicable to general number codes derived from the unimodular conversion having no constant-sums. In the case of generation of any erroneous operation in an adding circuit, the proposed detection of error can be executed by simple search of the constant-sum of the output since any constant-sum shown in Formula 8 will not be established due to the constant-sum unimodular p-acid number being employed therewith.

Further, if an indication system of the negative number by the principle of complement being utilized of the present adding circuit, a subtracting circuit can be easily con structed. And in order to expedite the operating speed, a circuit of high speed carry may be easily constructed.

Further, with use of the circuits such as shift circuit, multiplication table circuits and other supplemental circuits, there can be performed arithmetical operations (addition/subtraction/multiplication/division) which circuits can be also constructed by the use of conventional methods.

Thus, in order to construct a computing circuit capable of operating more complicated computations, the theory of the construction of the adding circuit in the present invention can be applied by means of an arrangement of the arithmetic operation. In addition, there is no necessity for supplementing any surplus circuit for executing the detection of error in the computing circuit.

Next, in the case 12:3, namely in the case of 3-adic system, the embodiment of the present invention will be explained by actually using figures.

Let the given decimal numbers to 5 and 6. These numbers are 12 and 20 respectively if expressed according to the ordinary 3-adic system, because 5=l 3+2=12 and 6=2 3+0=20.

Now, we shall add a constant-sum digit to the right of the least significant digit of each of the above two ordinary 3-acid numbers. In the case of 3-adic system, any of the digits 0, 1 and 2 may be used, but in this example we shall use 0.

3-adic number having a constant- Decimal sum digit number 3-adic number attached Next, the 3-adic numbers to which constant-sum digits are attached are converted into zero-sum cyclic 3-adic numbers. This conversion is performed by circuits 3 and 3 of FIGS. 3 and 5 and explained by the Equation 6.

3-adic number having a Zero-sum constant cyclic sum digit 3-adio attached number 120 (x) 111 (X') 200 (y) 210 (y) The above conversion is performed according to the following operation. The most significant digit is moved from column to the right, without giving any change, to form the most significant digit of the new number. Next, in the left column, subtract the most significant digit from the digit on its right and write the difference in the right column in the adjacent place less significant next to the most significant digit. If the difference is negative, add 3 to it (in the case of 3-adic numbers) and obtain an algebraic sum and write it in the above place.

For the rest of digits, conduct similar calculations. In the generalized form, subtract the next most significant digit from the digit in the place concerned of the 3-adic number to which a constant-sum digit is attached and Write the difference in the corresponding position of the zero-sum cyclic 3-adic number. Repeat the process in order.

When illustrated by a diagram, the above-described process is as follows:

Now, the constant-sum character of the constant-sum cyclic p-adic numbers which is a characteristic of the present invention should be clear. The constant-sum character refers to the fact that in the above example ofconstant-sum cyclic 3-adic numbers, if the sum of the digits of each number is divided by 3, the remainder is always the same figure as the constant-sum digit which was attached to the number. In the case of constant-sum cyclic p-adic numbers, the above 3 may be substituted by the digit p.

In this example, since the constant-sum digit is 0, the

sum of the digits of the respective numbers can be divided by 3 without a remainder as demonstrated below.

The following will illustrate addition of the two decimal numbers of and 6 in accordance with the conventional ternary system and the zero-sum cyclic 3-adic system,

respectively. This fact will be further explained by circuits 5 of FIGS. 3 and 5 and FIG. D and Equation 15.

no remainder no remainder Conventional 3-adic system with zero Zero-sum cyclic 3-adic added system 120 (x)- 111 (x) (y)- 1 (3) M (c) carry digits- :10 (d) cyclic carry digits c It?) 122: (7.)

Here, we must pay attention to the fact that the cyclic carry digits d (1200) of the above zero-sum cyclic 3-adic number were converted to their existing form by the cyclic conversion vector of the corresponding ordinary 3-adic carry digits 0 (100), and the cyclic sum (z) of the digits of the number obtained as the result of addition (i.e., x'+yld) has the zero-sum property.

In the above, the constant-sum digit attached 3-adic number 1020 has been obtained from the zero-sum cyclic 3-adic number 1221 according to the following operations.

The most significant digit 1 which is in the 4th position is transferred without any change. For the 3rd position digit of the new 3-adic number, we shall obtain 1+2=0 by adding the 4th and 3rd digits of the zero-sum cyclic 3-adic number. For the 2nd position digit of the new 3-adic number, we shall obtain 1+2+2=2 by adding the 4th, 3rd and 2nd digits of the zero-sum cyclic 3-adic number. Similarly, the 1st position digit is the sum of all digits, that is, 1+2+2+1=0u As the constant-sum digit is determined to be 0 in the above example and further the sum of digits of zero-sum cyclic number 1221 obtained is 6 which is divisible by 3,

it is verified that the operation has been conducted correctly by the constant-sum digit attached 3-adic numbers.

In the above example, explanation was made with 3-adic numbers, but operation can be conducted with numbers of any integer p-adic. Also, it is not always necessary to select the constant-sum digit to be 0', which constant-sum digit may be any digit less than p 1.

In this case, if the remainder obtained by dividing the sum of the digits of a number by p is the same as the constant-sum digit and, when the obtained value is converted into an ordinary p-adic number, if the least significant digit is the same as the constant-sum digit, it is evident that the operation has been conducted correctly.

In the constant-sum cyclic p-adic number, if, for example, 0 is used in its constant-sum digit, it is called zerosum cyclic p-adic number, and, therefore, if 2 is used in its constant-sum digit, it is called 2-sum cyclic p-adic number.

Accordingly, the present invention is directed to a conversion circuit and computing circuit for constant-sum cyclic p-adic numbers where errors in the adder circuit are contained in the sum obtained by incorporating operations for automatic verification, and therefore there is no need for an error detecting circuit (excepting such an adder circuit as shown in, FIG. 2), as required by the prior art.

Returning now to the drawings, the present invention will be explained in detail.

FIG. 3 is a block diagram of the whole adder circuit of the present invention. The adder circuit of the present invention is constructed with circuits 1, 1 for converting an ordinary decimal number to a p-adic number, a computing circuit 2 for performing a carry of the p-adic number, circuits 3, 3' for converting a p-adic number to a constant-sum cyclic p-adic number, a circuit 4 for converting the carry number obtained from the circuit 2 to a constant-sum cyclic p-adic number, an adder circuit 5 used for the constant-sum cyclic p-adic numbers, a circuit 6 for converting the number obtained from circuit 5 back to an ordinary 3-adic number, a detection circuit 7 for detecting whether the number obtained is correct or not, and circuit 8 for converting the 3-adic number back to an ordinary decimal number.

Circuits 1, 1' used for converting an ordinary decimal number to a p-adic number and circuit 8 used for converting a p-adic number to an ordinary decimal number are publicly known.

The two numbers in the decimal system to be added are converted to their corresponding p-adic numbers (x 3 by publicly kno'wn conversion circuits 1, 1 and, after the constant-sum digit has been added, sent to circuits 3, 3. After the p-adic numbers x y have been converted to constant-sum acyclic p-adic numbers (x,', 3 by circuits 3, 3' they are sent to adder circuit 5.

0n the other hand, carry digit for the two numbers (x y converted to p-adic number is performed by circuit 2, and, after the constant-sum digit has been added, the carry digit (Ci) is converted to a consant-sum cyclic p-adic number (d and sent to circuit 5.

The value (Z obtained by circuit 5 is converted back to an ordinary p-adic number (Zi) by circuit 6 and constant-sum digit is sent to circuit 7 as a checker where a check is made as to whether or not the calculation is correct.

The ordinary p-adic number (Zi) is converted to an ordinary decimal number by a conventional circuit, and the sum of the two numbers is obtained.

FIG. 4 is a symbolic circuit of an embodiment of an adder circuit for adding two input constant-sum cyclic p-adic numbers each having three digits. Block circuits 2, 4 and 5 correspond to the block circuits 2, 4 and 5 in FIG. 3 respectively.

FIG. 5 (A) is an embodiment of the conversion circuit in the parallel mode in which a p-adic number is converted into a constant-sum cyclic p-adic number and FIG. 5(B) is an embodiment of the conversion circuit in the serial mode of FIG. 5 (A).

FIG. 6 is an embodiment of the circuit for converting a constant-sum cyclic p-adic number into a p-adic number.

FIG. 7 is an example of relay contact matrix in 3-adic system according to the present invention. The matrix is used to construct the block circuits in FIGS. 4, 5 and 6, that is, a 3-adic adder circuit, a circuit for converting constant-sum cyclic 3-adic number into a 3-adic number.

FIG. 8 shows an example of relay contact matrix in S-adic system and, upon an application of this matrix to the block circuits in FIGS. 4, 5 and 6, a S-adie adder circuit, a circuit for converting a S-adic number into a constant-sum cyclic S-adic number and a circuit for converting a constant-sum cyclic S-adic number into a S-adic number are obtained.

FIG. 9 is a detection circuit for checking whether or not the calculation is correct with constant-sum digit added in converting the constant-sum cyclic p-adic number back to p-adic number.

FIG. 10 is an example of the present whole system of FIG. 3, each of the block circuits being constructed with the contact matrix circuit of FIG. 7.

As an example, it is assumed that an addition of decimal numbers 5 and 6 is performed in the system of FIG. 10.

A 3-adic number 12 which is converted from the decimal number by conventional decimal-ternary conversion circuit is added a constant-sum digit 0 at the right of the last significant digit 2, and thus a S-adic number 120 is produced. The respective digits of the 3-adic number 120 are referred as x x and x1- In FIG. (A), input contacts corresponding to the digit x are closed by energizations of relays of conventional decimal-ternary conversion circuits and, in this case, the contact x =1 is closed thereby a relay x =1 being energized to provide an output of x (the left circuit in FIG. 10(A)).

Upon the receipt of the next input digit 2, an input contact x =2 is closed, while contacts 11 of the contact matrix x for the next digit are closed by the closure of the contact x =1 of the preceding stage, and accordingly, the relay x is energized to provide an output x =|1. For the constant-sum digit 0, an input contact x- =0 of the third stage is closed, while contacts 2 of the third matrix are closed simultaneously with the closure of input contact of the second stage, and accordingly a relay xis energized to provide an output x'- Thus x- =1, x =1 and x' =1 are obtained as outputs of the circuits of FIG. 10(A) which corresponds to the block circuit in FIG. 3 and the 111 represents the 3-adic number 120 in the present constant-sum cyclic 3-adic system.

Similarly, the respective digits of 200, which is obtained by converting the decimal number 6 to a 3-adic number 20 and adding a constant-sum digit 0 to the right of the last significant digit 0, energize contacts y y and in FIG. 10(B) which corresponds to the block circuit 3' in FIG. 3. Consequently, relays y =2, y' =1 and y =0 are energized and thus a zero-sum cyclic 3-adic number 210 is obtained.

On the other hand, the relay contacts x =l, x =2, x- '=O, y =2, y =0 and y =0 are closed correspondingly to the closure of the input contacts in FIGS. 10(A) and 10(B) thereby electric currents being flow along the thick solid lines as shown in FIG. 10(C) which corresponds to the block circuit 2 in FIG. 3 and consequently relays C =1, C =0 and C =0,are energized.

The contacts in a part enclosed by dotted line in FIG. 10(D) correspond to the block circuit 4 in FIG. 3. A carry digit of 3-adic number obtained from the matrix in FIG. 10(0) is converted to a constant-sum 3-adic number in the circuit in FIG. 10(D). This conversion is performed by closing certain contacts in FIG. 10(D) upon energization of the relays C =1, C =0 and C :0 in FIG. 110(C).

Thus, the respective digits of the converted constantsum cyclic 3-adic number set the corresponding contacts enclosed by dotted line in FIG. 10(D) and at that time contacts x and y in FIG. 10(D) are closed correspondingly to the closure of the corresponding contacts in FIG. 10(A) and 10(B).

Consequently, electric currents are flown along the thick solid lines and thus relays Z' =1, Z' =2, Z 2 and Z :'1 are energized to provide an addition of two zerosum cyclic 3-adic numbers 210 and 120.

In FIG. 10(E) which corresponds to the block circuit 6 in FIG. 3, relay contacts Z' =1, Z' =2, Z 2 and Z' =1 which correspond to the digits of Z obtained from FIG 10(D) are closed and thus Z =1, Z :=O, and Z =2 are obtained through the closed contacts respecv tively.

dicating terminal and indicates that the result of calculation is correct.

The above description has been mentioned for an explanatory purpose of the adding circuit, however, any computing circuit (addition/subtraction/multiplication/ division) can be realized by basically utilizing such adding circuit. At the same time, the circuit still maintains the more advantageous feature of error detection.

Although it has embodied the parallel addition circuit of the three digital system, it is available to construct a serial adding circuit by utilizing a delay circuit.

Still another feature of the present method also allows the realization of various possibilities such as, for example, any finite positive integer other than 3 as a value of p and any finite positive other than 3 as a value of being applicable.

Furthermore, various components (mechanical, electrical, electronical) other than electrical relay devices can be also applied to the present system. In the case of coding the p-adic numbers, any code system such as a 2-adic number system may also be available according to the present invention.

In short, according to the present invention, in the computing circuit of the information processing device, the weighted sum modulo p of the respective digits of a number is made to have a constant value by means of applying number codes of the constant-sum cyclic p-adic system which was derived by the linear transformation on the integer modulo p represented by the matrices on the p-adic number to which is added 1 or many digits equal to the constant value other than the respective digits of the ordinary representation of the p-adic number. Accordingly, a number code of the ordinary p-adic number is converted by the conversion circuit which was merely constructed by an addition and subtraction circuit modulo p in which spatial and temporal cyclic characteristics are utilized together with another circuit of the multiplication table.

In this sense, the proposed conversion circuit and computing circuit including subtraction, multiplication and division incorporated with the theory of complement, circuit of multiplication table and division incorporated with the theory of complement, circuit of multiplication table and shift circuit are constructed With the knowledge of the adder of 2 numbers which are represented by the constant-sum cyclic p-adic number producing answers represented by the same cyclic p-adic number system, and the i digit of the sum is made equivalent with the sum modulo p of the three digits of the i digits augend and the addend together with the carry from the i digits.

According to the present invention, various kinds of number codes including the p-adic number can be selectively applied depending upon the purpose of computing so that construction of any proposed circuit based on any number code is available, however, only computing devices using 2-adic number or 10-adic number system have heretofore been applied.

In addition, according to the present invention, supplemental circuits for detecting erroneous operation in the prior art apparatus are not necessary any more. Consequently, the construction of the device of the present invention is remarkably simplified and together having further features of simplicity of detecting a computing operation as well as having the best reliability.

Accordingly, the calculating circuits according to the present invention should be widely utilized in the industrial field and particularly for manufacturers and .users of information processing devices, measuring devices, regulating devices, etc. including electronic computing machines.

I claim:

1. An addition/subtraction/multiplication/division circuit comprising:

means for converting two numbers of decimal system to be computed into ordinary p-adic numbers, respectively,

means for converting said ordinary p-adic numbers into constant-sum cyclic p-adic numbers, respectively, after attaching constant-sum digits to each of said ordinary p-adic numbers,

means for computing using said constant-sum cyclic p-adic numbers to obtain a computed constant-sum cyclic p-adic number,

means for detecting whether computation is conducted correctly by verifying whether the sum of the digits of said computed constant-sum cyclic number corresponds to said constant-sum digits attached,

means for converting said computed constant-sum cyclic p-adic number into its corresponding ordinary p-adic number,

means for converting said correspondingly ordinary p-adic number into its corresponding decimal number.

2. The circuit, as set forth in claim 1, wherein said constant-sum digits to be attached are less than the p-adic number to be used.

3. The circuit, as set forth in claim 1, wherein said mean for detecting comprises:

means for conducting detection while converting said computed constant-sum cyclic p-adic number into ordinary p-adic number. 4. The circuit, as set forth in claim 1, wherein: said means for detecting comprises means for adding the digits of said computed constant-sum cyclic p-adic number and then dividing the result by the p-adic number to determine if the remainder is the same as said constant-sum number attached.

5. The circuit, as set forth in claim 1, further comprising:

means for computing a cyclic p-adic carry number from the carry digits of a sum of said ordinary p-adic numbers, and

said means for computing said computed constant-sum cyclic p-adic number adds said constant-sum cyclic p-adic numbers and said cyclic p-adic carry number.

References Cited UNITED STATES PATENTS 3,436,755 4/ 1969 Tolman 340--347 FOREIGN PATENTS 1,187,831 2/ 1965 Germany.

MALCOLM A. MORRISON, Primary Examiner R. s. DILDINE, Jr.,Assistant Examiner us. 01. X.R. 

